Features Configuration Bits RAM map SFR map

PIC18LF8585
CONFIG1H (address:0x300001, mask:0x2F, default:0x2F)
OSC -- Oscillator (bitmask:0x0F)
OSC = LP | 0xF0 | LP oscillator.
OSC = XT | 0xF1 | XT oscillator.
OSC = HS | 0xF2 | HS oscillator.
OSC = RC | 0xF3 | RC oscillator with OSC2 configured as divide by 4 clock output.
OSC = EC | 0xF4 | EC oscillator with OSC2 configured as divide by 4 clock output.
OSC = ECIO | 0xF5 | EC oscillator with OSC2 configured as RA6.
OSC = HSPLL | 0xF6 | HS oscillator with HW enabled 4x PLL.
OSC = RCIO | 0xF7 | RC oscillator with OSC2 configured as RA6.
OSC = ECIOPLL | 0xFC | EC oscillator with OSC2 configured as RA6 and HW enabled 4x PLL.
OSC = ECIOSWPLL | 0xFD | EC oscillator with OSC2 configured as RA6 and SW enabled 4x PLL.
OSC = HSSWPLL | 0xFE | HS oscillator with SW enabled 4x PLL.
OSCS -- Osc. Switch Enable (bitmask:0x20)
OSCS = ON | 0xDF | Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled).
OSCS = OFF | 0xFF | Oscillator system clock switch option is disabled (main oscillator is source).
CONFIG2L (address:0x300002, mask:0x0F, default:0x0F)
PWRT -- Power Up Timer (bitmask:0x01)
PWRT = ON | 0xFE | PWRT enabled.
PWRT = OFF | 0xFF | PWRT disabled.
BOR -- Brown Out Detect (bitmask:0x02)
BOR = OFF | 0xFD | Brown-out Reset disabled.
BOR = ON | 0xFF | Brown-out Reset enabled.
BORV -- Brown Out Voltage (bitmask:0x0C)
BORV = 45 | 0xF3 | VBOR set to 4.5V.
BORV = 42 | 0xF7 | VBOR set to 4.2V.
BORV = 27 | 0xFB | VBOR set to 2.7V.
BORV = 20 | 0xFF | VBOR set to 2.0V.
CONFIG2H (address:0x300003, mask:0x1F, default:0x1F)
WDT -- Watchdog Timer (bitmask:0x01)
WDT = OFF | 0xFE | WDT disabled (control is placed on the SWDTEN bit).
WDT = ON | 0xFF | WDT enabled.
WDTPS -- Watchdog Postscaler (bitmask:0x1E)
WDTPS = 1 | 0xE1 | 1:1.
WDTPS = 2 | 0xE3 | 1:2.
WDTPS = 4 | 0xE5 | 1:4.
WDTPS = 8 | 0xE7 | 1:8.
WDTPS = 16 | 0xE9 | 1:16.
WDTPS = 32 | 0xEB | 1:32.
WDTPS = 64 | 0xED | 1:64.
WDTPS = 128 | 0xEF | 1:128.
WDTPS = 256 | 0xF1 | 1:256.
WDTPS = 512 | 0xF3 | 1:512.
WDTPS = 1024 | 0xF5 | 1:1024.
WDTPS = 2048 | 0xF7 | 1:2048.
WDTPS = 4096 | 0xF9 | 1:4096.
WDTPS = 8192 | 0xFB | 1:8192.
WDTPS = 16384 | 0xFD | 1:16384.
WDTPS = 32768 | 0xFF | 1:32768.
CONFIG3L (address:0x300004, mask:0x83, default:0x83)
MODE -- Processor Mode (bitmask:0x03)
MODE = EM | 0xFC | Extended Microcontroller mode.
MODE = MPB | 0xFD | Microprocessor with Boot Block mode.
MODE = MP | 0xFE | Microprocessor mode.
MODE = MC | 0xFF | Microcontroller mode.
WAIT -- External Bus Wait (bitmask:0x80)
WAIT = ON | 0x7F | Wait selections for table reads and table writes are determined by WAIT1:WAIT0 bits (MEMCOM<5:4>).
WAIT = OFF | 0xFF | Wait selections unavailable for table reads and table writes.
CONFIG3H (address:0x300005, mask:0x83, default:0x83)
CCP2MX -- CCP2 Mux (bitmask:0x01)
CCP2MX = OFF | 0xFE | CCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode.
CCP2MX = ON | 0xFF | CCP2 input/output is multiplexed with RC1.
ECCPMX -- ECCP Mux (bitmask:0x02)
ECCPMX = PORTH | 0xFD | P1B, P1C are multiplexed with RH7, RH6.
ECCPMX = PORTE | 0xFF | P1B, P1C are multiplexed with RE6, RE5.
MCLRE -- MCLR enable (bitmask:0x80)
MCLRE = OFF | 0x7F | RG5 input enabled, MCLR disabled.
MCLRE = ON | 0xFF | MCLR pin enabled, RG5 input pin disabled.
CONFIG4L (address:0x300006, mask:0x85, default:0x85)
STVR -- Stack Overflow Reset (bitmask:0x01)
STVR = OFF | 0xFE | Stack full/underflow will not cause Reset.
STVR = ON | 0xFF | Stack full/underflow will cause Reset.
LVP -- Low Voltage Program (bitmask:0x04)
LVP = OFF | 0xFB | Low-voltage ICSP disabled.
LVP = ON | 0xFF | Low-voltage ICSP enabled.
DEBUG -- Background Debugger Enable bit (bitmask:0x80)
DEBUG = ON | 0x7F | Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug.
DEBUG = OFF | 0xFF | Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins.
CONFIG5L (address:0x300008, mask:0x07, default:0x07)
CP0 -- Code Protect 000800-0003FFF (bitmask:0x01)
CP0 = ON | 0xFE | Block 0 (000800-003FFFh) code-protected.
CP0 = OFF | 0xFF | Block 0 (000800-003FFFh) not code-protected.
CP1 -- Code Protect 0004000-007FFF (bitmask:0x02)
CP1 = ON | 0xFD | Block 1 (004000-007FFFh) code-protected.
CP1 = OFF | 0xFF | Block 1 (004000-007FFFh) not code-protected.
CP2 -- Code Protect 008000-00BFFF (bitmask:0x04)
CP2 = ON | 0xFB | Block 2 (008000-00BFFFh) code-protected.
CP2 = OFF | 0xFF | Block 2 (008000-00BFFFh) not code-protected.
CONFIG5H (address:0x300009, mask:0xC0, default:0xC0)
CPB -- Code Protect Boot (bitmask:0x40)
CPB = ON | 0xBF | Boot block (000000-0007FFh) code-protected.
CPB = OFF | 0xFF | Boot block (000000-0007FFh) not code-protected.
CPD -- Data EE Read Protect (bitmask:0x80)
CPD = ON | 0x7F | Data EEPROM code-protected.
CPD = OFF | 0xFF | Data EEPROM not code-protected.
CONFIG6L (address:0x30000A, mask:0x07, default:0x07)
WRT0 -- Table Write Protect 00800-003FFF (bitmask:0x01)
WRT0 = ON | 0xFE | Block 0 (000800-003FFFh) write-protected.
WRT0 = OFF | 0xFF | Block 0 (000800-003FFFh) not write-protected.
WRT1 -- Table Write Protect 004000-007FFF (bitmask:0x02)
WRT1 = ON | 0xFD | Block 1 (004000-007FFFh) write-protected.
WRT1 = OFF | 0xFF | Block 1 (004000-007FFFh) not write-protected.
WRT2 -- Table Write Protect 08000-0BFFF (bitmask:0x04)
WRT2 = ON | 0xFB | Block 2 (008000-00BFFFh) write-protected.
WRT2 = OFF | 0xFF | Block 2 (008000-00BFFFh) not write-protected.
CONFIG6H (address:0x30000B, mask:0xE0, default:0xE0)
WRTC -- Config. Write Protect (bitmask:0x20)
WRTC = ON | 0xDF | Configuration registers (300000-3000FFh) write-protected.
WRTC = OFF | 0xFF | Configuration registers (300000-3000FFh) not write-protected.
WRTB -- Table Write Protect Boot (bitmask:0x40)
WRTB = ON | 0xBF | Boot block (000000-0007FFh) write-protected.
WRTB = OFF | 0xFF | Boot block (000000-0007FFh) not write-protected.
WRTD -- Data EE Write Protect (bitmask:0x80)
WRTD = ON | 0x7F | Data EEPROM write-protected.
WRTD = OFF | 0xFF | Data EEPROM not write-protected.
CONFIG7L (address:0x30000C, mask:0x07, default:0x07)
EBTR0 -- Table Read Protect 00800-003FFF (bitmask:0x01)
EBTR0 = ON | 0xFE | Block 0 (000800-003FFFh) protected from table reads executed in other blocks.
EBTR0 = OFF | 0xFF | Block 0 (000800-003FFFh) not protected from table reads executed in other blocks.
EBTR1 -- Table Read Protect 004000-07FFF (bitmask:0x02)
EBTR1 = ON | 0xFD | Block 1 (004000-007FFFh) protected from table reads executed in other blocks.
EBTR1 = OFF | 0xFF | Block 1 (004000-007FFFh) not protected from table reads executed in other blocks.
EBTR2 -- Table Read Protect 08000-0BFFF (bitmask:0x04)
EBTR2 = ON | 0xFB | Block 2 (008000-00BFFFh) protected from table reads executed in other blocks.
EBTR2 = OFF | 0xFF | Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks.
CONFIG7H (address:0x30000D, mask:0x40, default:0x40)
EBTRB -- Table Read Protect Boot (bitmask:0x40)
EBTRB = ON | 0xBF | Boot block (000000-0007FFh) protected from table reads executed in other blocks.
EBTRB = OFF | 0xFF | Boot block (000000-0007FFh) not protected from table reads executed in other blocks.

This page generated automatically by the device-help.pl program (2016-08-21 09:07:44 UTC) from the 8bit_device.info file (rev: 1.31) of mpasmx and from the gputils source package (rev: svn Unversioned directory). The mpasmx is included in the MPLAB X.